A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival
نویسندگان
چکیده
An efficient parallel adder under left-to-right input arrival is proposed. Making full use of the delay of the input arrival, it produces the sum within a small constant delay after the arrival of the final bits. Its amount of hardware is proportional to the operand length. It can be applied to the quotient conversion in an array divider.
منابع مشابه
Constant Delay Linear Size Adder under Left-to-Right Input Arrival
A parallel adder which is optimal in both delay and size under left-to-right input arrival is proposed. The delay is the computation time after the arrival of the nal input bits. The proposed adder is composed of a carry select adder (CSA) and a small adder based on the on-they conversion (OTFA). Parallel computation in the CSA and the OTFA which make full use of the delay of the input arrival ...
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عنوان ژورنال:
- IEEE Trans. Computers
دوره 48 شماره
صفحات -
تاریخ انتشار 1999